This invention relates in general to a system and method for controlling material removal rates during polishing; and, in particular, for controlling thickness removal during chemical mechanical polishing using detection, statistical estimation, and time series analysis.
Increasingly, chemical mechanical polishing (CMP) is becoming the methodology of choice to polish certain articles of manufacture that require a desired degree of planarization, such as semiconductor wafers from which chips for integrated circuits are processed. Generally, CMP employs a polishing system for processing such a wafer by polishing on one surface thereof by a procedure which includes engagement of the semiconductor wafer face with a polishing pad and a method of controlling such polishing.
Typically, integrated circuits are provided as xe2x80x9cchipsxe2x80x9d, each of which includes a slice of a flat material that has the specific circuitry. A multiple number of the desired integrated circuits are formed at the same time by etching and coating a disk-shaped semiconductor wafer substrate. The wafer is then diced into flat rectangles which are individually provided with suitable packaging having the necessary leads to electrically access the integrated circuitry. In certain instances a full wafer is used to form a single integrated circuit rather than duplicates of a desired integrated circuit.
The disk-shaped wafer substrates typically are comprised of a monocrystalline semiconductor, such as single crystal silicon. One common method of forming the wafer is to grow a relatively long cylinder or log of a single crystal of the material, and then slice the log (often called a boule) to form the individual disk-shaped wafers.
It is necessary for the formation of various circuits or for other uses of wafers, that the active or front face, e.g., the face of the wafer on which the integrated circuitry is to be formed, be highly polished. (The other side of the wafer is often referred to as the wafer xe2x80x9cbackxe2x80x9d face.)
At the beginning of a chemical mechanical polishing (CMP) step for ILD (inter-layer dielectric) planarization at time t0, the difference in top surface height, hinitial, between the field region and areas of dense device features may be as large as 0.8 to 1.0 micro meter. Pre-CMP semiconductor thickness measurements arc used to determine the polishing time (tfinal) for each wafer based on calibrations established in the development stage. At time t0, the polisher starts to remove material, typically at a rate of 1-3 kA/minute, but faster on features that are smaller and isolated, and more slowly on features that are larger or in densely packed areas.
Polishing continues through until time (tfinal) when the wafer is removed from the tool, cleaned, and measured afterwards to confirm that an acceptable final thickness (tfinal) was achieved.
The final thickness measurement is an important moment for CMP metrology. The time (tfinal) is selected from a CMP polisher calibration based on applied pressure, rotation speed, average pad life degradation, pressure, etc., to produce a (tfinal) centered within the allowed semiconductor wafer process window. However, dynamic factors may alter the actual thickness (Ttrue) realized at time (tfinal). If the material removed by time (tfinal) exceeds the limit, the wafer must be scrapped or more dielectric must be deposited. If the remaining thickness is excessive, the wafer can be returned to the polisher for rework. This above-described loop characterizes the basic CMP method today.
The CMP process window is defined as the difference between the Upper And Lower Thickness Limits (TUL and TLL). The CMP tool design must completely eliminate malfunctions that can cause large thickness errors.
During semiconductor wafer fabrication, silicon is plasma-etched to form device islands, then thin oxide and silicon nitride layers are deposited. Dielectric material (TEOS) is deposited to fill the spaces between the islands and build up a thick dielectric over-layer. CMP tools then planarize the upper surface of this dielectric layer, eventually polishing through the TEOS and exposing the underlying SiN at some locations. Since SiN has a removal rate several times smaller than oxide, the polishing slows at the exposed locations, allowing slower areas to xe2x80x9ccatch-upxe2x80x9d for improved planarity.
Since the SiN removal rate is smaller but still non-zero, it is important to measure the thickness of the remaining oxide and nitride simultaneously. Otherwise, the remaining SiN layer could become too thin at the location where the polish is fastest.
Other semiconductor wafer CMP operation issues include global planarity which are dominated by the xe2x80x9cmacroxe2x80x9d effects of the polisher pad, wafer head chucking device, polish pad velocity, polishing pad age and conditioning, etc. Uniformity from wafer center to wafer edge is the usual metric. Across-the-wafer uniformity is also influenced by boundary effects at device edges, at the wafer edge. CMP tools must provide thickness measurement that can accommodate custom spaced measurements of chosen length and point density in diameter or radius scan format. CMP operations on semiconductor device features with large spatial separations reveal several surprising effects.
First, an effect known as the xe2x80x9cedge effectxe2x80x9d can cause a thicker oxide in the outer 5-15 mm of the wafer. The excess thickness can range from 1-4 kA depending on the manner in which the wafer is held in the polishing carrier. A second unexpected effect visible in the figure is the oscillation in thickness across the wafer. This 100-200A variation occurs because the CMP TEOS polishing rate is faster in the kerf area adjacent to the test die than in the kerf intersection areas.
Within-die planarity is influenced by the tendency of CMP to polish smaller, individual features faster, and larger and densely-packed features more slowly. The oxide removal rate over features of 15 micro meter width was 60-80% greater than over features of 65 micro meter width under high throughput conditions. This effect introduces considerable complexity, given the differences in pattern density that occur on IC devices.
CMP processing reaches an asymptotic limit in the microplanarity regime, where polishing occurs largely by smoothing and filling-in between the dense, small features, rather than by direct removal of material from larger spacing.
These effects concerning semiconductor device feature size subsequently drive a subordinate requirement that CMP tools automatically perform a sequence of semiconductor wafer film thickness measurements and manage the data from different semiconductor device features accordingly. Each semiconductor device site job file becomes a chain of individual measurements, each with its own location, measurement recipe, pattern recognition model, and data format.
The semiconductor wafer film thickness measurement data generated may be needed in processing according to device feature type and size, as well as locations on the wafer. The CMP tool operator must simultaneously keep within limits the thickness at the smallest, fastest-polishing feature within the fastest-polishing die on the wafer, and at the largest, slowest-polishing feature in the slowest polishing die on the wafer.
To this end, chemical mechanical polishing machines have been designed to provide the desired semiconductor device film thickness. The machine typically brings the device face of the wafer to be polished into engagement with a polishing surface such as the polishing surface of a pad having a desired polishing material, e.g., a slurry of colloid silica, applied thereto.
The movement between the wafer and the polishing pad provides the polishing As forces. In some instances, this xe2x80x9cpolishingxe2x80x9d is provided primarily for the purpose of making one face flat, or parallel to another face. In this connection, it must be remembered that the wafer itself is microcrystalline and characteristics of this type may be quite important in making the wafer suitable for the production of integrated circuitry or for some other desired use.
An abrasive, proportionately dispensed in the slurry, provides the cutting action when the wafer is engaged by pressure and placed in contact with a polishing pad laden with the slurry/abrasive mixture, and then caused to move laterally relative to the polishing pad. It is further recognized that the repeated engagement of the faces of numerous wafers moving against the polishing pad will result in a wearing out of the polishing pad over a described period of time. The resultant wearing out of the polishing pad therefor has an undesirable effect on the consistency of the surface finish of the wafer prescribed under the terms of Preston""s equation, since, in general, a longer polishing time on a worn polishing pad will be required to achieve the same thickness of removal that can be accomplished on a new polishing pad in a significantly shorter time.
Preston""s equation states:
xe2x80x83Removal Rate=(xcex94m/xcex94t)=xcex94mt=[(KP(P*V)*(A/Ac,*xcex94t2)]
whereas:
Further it is understood the term KP (Preston""s constant) is composed of the complex parameters Ka and Kb, wherein:
Ka is the roughness and elastic constant of the polishing pad, and
Kb is the complex term for the surface chemistry and abrasive material used in the slurry.
Accordingly, there is a need for a control or compensation for constantly varying results which are achieved over time during a polishing series, given a fixed set of polishing variables, due to degradation of the polishing surface and polishing media, among other variables.
It is an object of the present invention to provide a chemical mechanical polishing system that first measures an unprocessed semiconductor wafer, tinitial, then during the subsequent CMP operation, statistically corrects for the resultant wearing out of the semiconductor wafer polishing pad. This is accomplished by a first wafer thin film measurement means which provides tinitial, then performing a correction/learning CMP operation on said wafer by feeding forward the amount of film to be removed during said CMP with a linear prediction and estimation factor constructed from previously performed wafer CMP operations including a (tfinal) thickness measurement on said previous semiconductor wafer. This operational sequence thus nullifies the undesirable effects of film consistency variations on the device surface of said semiconductor wafer.
Another object of this invention is to provide a method and apparatus for a computer controlled function, sampling the data from an external thin film thickness measurement device and adding a statistical signal processing algorithm using analysis and prediction of the current and future removal rates based on performance of past ratios of the before and after CMP processing of semiconductor film thickness readings.
Further, it is yet another object of this invention to have a chemical mechanical polishing system that statistically corrects for the resultant transformation of the polishing characteristics of the polishing system by the use a linear estimation factor thus nullifying the undesirable effects of said polishing pad non-consistency upon the surface finish of the wafer. This algorithmic procedure provides a chemical mechanical polishing system a stable means of removal control for a specific thickness dimension of certain layered materials from the uppermost overlay of a semiconductor wafer.
These and other objects of the invention will become apparent upon referencing the descriptions, drawings, and detail of the preferred embodiments herein.
Thus, a method for controlling thickness removal of a substrate during polishing of a series of n substrates, where n is a positive integer greater than one is disclosed to include: measuring a thickness of a first substrate prior to polishing; polishing the first substrate for a predetermined time; measuring the thickness of the first substrate after polishing; determining an actual thickness removal rate, based on the measurement before, the measurement after and the predetermined time; and applying a linear estimation factor, based on the actual thickness removal rate, to form an adjusted polishing time for a subsequent substrate to be polished, to adjust for degradation and inconsistency of a polishing surface that occurs during the polishing of multiple substrates.
Further, the method includes measuring a thickness of the subsequent substrate prior to polishing; polishing the second substrate for the adjusted polishing time; measuring the thickness of the subsequent substrate after polishing; determining an actual thickness removal rate, based on the measurements of the subsequent substrate before and after polishing and the adjusted polishing time; and applying a linear estimation factor, based on the actual thickness removal rates of previously polished and measured substrates, to form an adjusted polishing time for a subsequent substrate to be polished, to adjust for degradation and inconsistency of a polishing surface that occurs during the polishing of multiple substrates.
This process is repeated for subsequent substrates up to n. The linear estimation factor is disclosed as taking into account measurement and polishing data of up to ten previous substrates for forming a linear estimation factor for the next subsequent substrate to be polished. Preferably, the estimation factor is determined using a Yule-Walker algorithm, although other algorithms may possibly be used.
Preferably, the polishing process is a chemical mechanical polishing process, although the invention may be applied to other polishing processes. The adjustment of polishing time according to the linear estimation factor compensates for polishing pad inconsistencies over the course of polishing a series of substrates.
An apparatus for controlling thickness removal of substrates during polishing of a series of substrates is disclosed to include: a polisher having a polishing surface, a substrate carrier for pressing a substrate against said polishing surface with a controlled pressure, and at least one driver for moving the substrate carrier and substrate along the polishing surface to effect a polishing of the substrate; a thickness measuring device for measuring a thickness dimension of the substrate before and after polishing; and means for determining an actual thickness removal rate, based on the measurements of the substrate before and after polishing and a time of polishing the substrate, and for determining a linear estimation factor, based on the actual thickness removal rate, to form an adjusted polishing time for a subsequent substrate to be polished, to adjust for degradation and inconsistency of a polishing surface that occurs during the polishing of multiple substrates.
Preferably, the polisher is a chemical mechanical polisher and the polishing surface includes an abrasive slurry. Preferably the substrates to be polished are semiconductor wafers.
Finally, an apparatus for compensating for polishing surface degradation is disclosed to include a thickness measuring device for measuring a thickness dimension of a substrate to be polished both before and after polishing; and means for determining an actual thickness removal rate, based on the measurements of the substrate before and after polishing and a time of polishing the substrate, and for determining a linear estimation factor, based on the actual thickness removal rate, to form an adjusted polishing time for a subsequent substrate to be polished, to adjust for degradation and inconsistency of a polishing surface that occurs during the polishing of multiple substrates.